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Re: Takes two day for my post to show up

 

AG wrote:

? ?"Yahoo hs lost a lot of people and Verizon is not bothering to sign reqs to replace them..."

Why would Verizon have anything to do with jobs at a different company that they do not manage?

I think it's 'jumping the gun' quite a bit to expect Verizon to micro-manage a separate company they do not control.? Assuming that the purchase will be approved (in my future, I assume yours too), then Verizon would take ownership in 2017, and could start making management decisions.? My calendar still says 2016.? We're not there yet.

If there are unfilled jobs at Yahoo now, it is Yahoo's responsibility to handle them now.? Nobody else's.

Yahoo never had a good track record for support, now or 5 years ago.? We were complaining then about not having (e.g., hiring) employees in the right places.

But again, this is WAAAAY off-topic here.

(As for Yahoo Messenger, my personal opinion is to say "thank goodness, it's about time." ?It didn't work right, a lot of time it didn't work at all.? I think I'm glad Yahoo figured that out.? Again, Yahoo.? NOT Verizon, not Intel, not BP, not LTC.)

Andy
Re: PMBFJ620/2SK2145 or any other dual JFET-models exist for LTspice?

 

Are there sny more around perhaps? Can't seem to find these in any shops.
Re: Probing phase

 

Hello Steve

The error
" Error on line 101 : q13 n053 n062 vout-darlpp 0 qd44vh10 " appears because you have a bad

.SUBCKT 2SC6144SG 1 2 3 finishing by
.ensL

Correct .endL in .endS and your circuit will run.

It's not so obvious.

Regards
PhB
Re: Probing phase

Steve Kale
 

¿ªÔÆÌåÓý

Hi

I have added Reg Circuits.zip to the Temp files folder. ?It contains (1) the (old) reg circuits.asc file which has the problem you are exploring (just change the subcircuit Spice directive between a Spice directive and comment to see the error behaviour) plus (2) the log file and (3) Qd45vh10.txt which I believe is the only file missing to enable reg circuits.asc to run if ?both files are added to the folder I uploaded previously (Phase Analysis Rev B.zip). (You will see that Darlington.asc is basically just the bottom two schematics in reg circuits.asc with minor amendments.)

Thanks

Steve


On 9 Aug 2016, at 16:31, basier.philippe@... [LTspice] <LTspice@...> wrote:

Hello Steve

"?I have pasted below the log file I get when (a) the 2SC6144SG subcircuit Spice directive is not made a comment?"

Coul you set "generate expanded listing" in control Panel \ Operatons and send again the file .log ?
Don't cancel the run.?
Upload in Temp it if it is too big.

" q13 n053 n062 vout-darlpp 0 qd44vh10" :


Regards
PhB
Re: Probing phase

 

Hello Steve

" I have pasted below the log file I get when (a) the 2SC6144SG subcircuit Spice directive is not made a comment "

Coul you set "generate expanded listing" in control Panel \ Operatons and send again the file .log ?
Don't cancel the run.
Upload in Temp it if it is too big.

" q13 n053 n062 vout-darlpp 0 qd44vh10" :


Regards
PhB
Re: Probing phase

Steve Kale
 

I tracked this down to a missing resistor. Stupid. ?Now off to the opticians for a new set of glasses¡­

I¡¯ve updated the zip file in the Temp files section to Phase Analysis Rev B and deleted the old one.?


On 9 Aug 2016, at 11:32, Steve wrote:

Now, the sub 1kHz behaviour remains the same as the image I had uploaded in the zip file (i.e. different from my new circuit) so I need to track down what¡¯s causing that difference.
Re: Probing phase

Steve Kale
 

¿ªÔÆÌåÓý

Hi Philippe

I have pasted below the log file I get when (a) the 2SC6144SG subcircuit Spice directive is not made a comment and (b) I ¡°OK¡± through the errors rather than cancelling the run.

Thanks for the correction to the .subckt. ?I got this from the On Semi website. Could this be a Spice D vs LTspice translation issue or just error?


Note I also found I had to alter their pin order in the line beginning Q1. They had:

Q1 2 1 3 ?C6144SG

But I¡¯m not sure why this should give me the issue I encountered when the Spice directive wasn¡¯t even being called upon¡­

Regards

Steve

Circuit: * /Users/steve/Desktop/Spice Modelling/Sziklai AD817A/Reg Circuits.asc

Error on line 101 : q13 n053 n062 vout-darlpp 0 qd44vh10
Unable to find definition of model "qd44vh10"
Error on line 133 : q18 n092 n102 vout-darl 0 qd44vh10
Unable to find definition of model "qd44vh10"
Error on line 199 : q27 n123 n131 vout-darlpp2 0 qd44vh10
Unable to find definition of model "qd44vh10"
Error on line 236 : q33 n056 n066 vout-darlpp-stab 0 qd44vh10
Unable to find definition of model "qd44vh10"
Error on line 273 : q38 n095 n103 vout-darl-stab 0 qd44vh10
Unable to find definition of model "qd44vh10"
Error on line 315 : q41 n126 n134 vout-darlpp2-stab 0 qd44vh10
Unable to find definition of model "qd44vh10"
C81: Increased Cpar to 4.7e-10
C80: Increased Cpar to 4.7e-10
C79: Increased Cpar to 1e-09
C78: Increased Cpar to 1e-09
C72: Increased Cpar to 4.7e-10
C71: Increased Cpar to 4.7e-10
C70: Increased Cpar to 1e-09
C69: Increased Cpar to 1e-09
C63: Increased Cpar to 4.7e-10
C62: Increased Cpar to 4.7e-10
C61: Increased Cpar to 1e-09
C60: Increased Cpar to 1e-09
C54: Increased Cpar to 4.7e-10
C53: Increased Cpar to 4.7e-10
C52: Increased Cpar to 1e-09
C51: Increased Cpar to 1e-09
C43: Increased Cpar to 4.7e-10
C42: Increased Cpar to 4.7e-10
C41: Increased Cpar to 1e-09
C40: Increased Cpar to 1e-09
C34: Increased Cpar to 4.7e-10
C33: Increased Cpar to 4.7e-10
C32: Increased Cpar to 1e-09
C31: Increased Cpar to 1e-09
C25: Increased Cpar to 4.7e-10
C24: Increased Cpar to 4.7e-10
C23: Increased Cpar to 1e-09
C22: Increased Cpar to 1e-09
C17: Increased Cpar to 4.7e-10
C16: Increased Cpar to 4.7e-10
C15: Increased Cpar to 1e-09
C14: Increased Cpar to 1e-09
C7: Increased Cpar to 4.7e-10
C6: Increased Cpar to 4.7e-10
C5: Increased Cpar to 1e-09
C4: Increased Cpar to 1e-09
WARNING: Less than two connections to node D1:5. ?This node is used by R:D1:3.
WARNING: Less than two connections to node D2:5. ?This node is used by R:D2:3.
WARNING: Less than two connections to node D3:5. ?This node is used by R:D3:3.
WARNING: Less than two connections to node D4:5. ?This node is used by R:D4:3.
WARNING: Less than two connections to node D5:5. ?This node is used by R:D5:3.
WARNING: Less than two connections to node D6:5. ?This node is used by R:D6:3.
WARNING: Less than two connections to node D7:5. ?This node is used by R:D7:3.
WARNING: Less than two connections to node D8:5. ?This node is used by R:D8:3.
WARNING: Less than two connections to node D13:5. ?This node is used by R:D13:3.
WARNING: Less than two connections to node N158. ?This node is used by R127.
Early termination of direct N-R iteration.
Direct Newton iteration failed to find .op point. ?(Use ".option noopiter" to skip.)
Starting Gmin stepping
Gmin = 10
Gmin = 1.07374
Gmin = 0.115292
Gmin = 0.0123794
Gmin = 0.00132923
Gmin = 0.000142725
Gmin = 1.5325e-05
Gmin = 1.6455e-06
vernier = 0.5
vernier = 0.25
vernier = 0.125
Gmin = 7.68205e-07
vernier = 0.166667
vernier = 0.0833333
Gmin = 6.25527e-07
vernier = 0.111111
vernier = 0.148148
Gmin = 4.58853e-07
vernier = 0.197531
vernier = 0.263374
Gmin = 2.81252e-07
vernier = 0.351165
Gmin = 1.31537e-07
vernier = 0.46822
vernier = 0.624294
Gmin = 3.79017e-08
vernier = 0.832392
vernier = 1
Gmin = 5.83787e-09
Gmin = 6.26837e-10
Gmin = 6.73061e-11
Gmin = 0
Gmin stepping succeeded in finding the operating point.

Ignoring empty pin current: Ix(u2:11)
Ignoring empty pin current: Ix(u4:11)
Ignoring empty pin current: Ix(u6:11)
Ignoring empty pin current: Ix(u8:11)
Ignoring empty pin current: Ix(u10:11)
Ignoring empty pin current: Ix(u12:11)
Ignoring empty pin current: Ix(u14:11)
Ignoring empty pin current: Ix(u16:11)
Ignoring empty pin current: Ix(u18:11)
Ignoring empty pin current: Ix(u19:11)
Ignoring empty pin current: Ix(u2:11)
Ignoring empty pin current: Ix(u4:11)
Ignoring empty pin current: Ix(u6:11)
Ignoring empty pin current: Ix(u8:11)
Ignoring empty pin current: Ix(u10:11)
Ignoring empty pin current: Ix(u12:11)
Ignoring empty pin current: Ix(u14:11)
Ignoring empty pin current: Ix(u16:11)
Ignoring empty pin current: Ix(u18:11)
Ignoring empty pin current: Ix(u19:11)

Date: Tue Aug ?9 15:30:59 2016
Total elapsed time: 51.922 seconds.

tnom = 27
temp = 27
method = trap
totiter = 1287
traniter = 0
tranpoints = 0
accept = 0
rejected = 0
matrix size = 834
fillins = 1891
solver = Alternate
Matrix Compiler1: ? ?9656 opcodes
Matrix Compiler2: ? ?7661 opcodes


On 9 Aug 2016, at 15:27, philippe wrote:

Hello Steve

You wrote:
"??That plot was produced in an earlier schematic. I later encountered problems with the schematic no longer recognising .inc statements and hence refusing to work.?"

Have you still the .log file you got when you tried to run the earlier schematic ?

Note that in?
.SUBCKT 2SC6144SG 1 2 3
Q1 1 2 3? C6144SG???????????????????????????????????????????????????????????????
??????????????????????????????????????????????????????????????????????????????
.MODEL C6144SG npn (?????? IS?????? = 3.500p???????? BF?????? = 335???????????
+NF?????? = 1????????????? VAF????? = 9????????????? IKF????? = 13????????????
+ISE????? = 50.00p???????? NE?????? = 2????????????? BR?????? = 160???????????
+NR?????? = 1????????????? VAR????? = 26???????????? IKR????? = 2.9???????????
+ISC????? = 230.0p???????? NC?????? = 2????????????? RB?????? = 910.0m????????
+IRB????? = 100.0m???????? RBM????? = 22.20m???????? RE?????? = 20.50m????????
+RC?????? = 3.300m???????? XTB????? = 1.9??????????? EG?????? = 1.11??????????
+XTI????? = 3????????????? CJE????? = 1.420n???????? VJE????? = 750.0m????????
+MJE????? = 383.0m???????? TF?????? = 450p?????????? XTF????? = 7?????????????
+VTF????? = 1.000K???????? ITF????? = 20???????????? PTF????? = 0?????????????
+CJC????? = 230.0p???????? VJC????? = 520.0m???????? MJC????? = 418.0m????????
+XCJC???? = 1????????????? TR?????? = 1.000n???????? FC?????? = 500.0m????????
+KF?????? = 0????????????? AF?????? = 1????????????? )????????????????????????
*?????????????????????????????????????????????????????????????????????????????
.ENDL?2SC6144SG

.ENDL? should be ENDS

LTspice can't run with .endl

Regards
PhB
Re: Probing phase

 

Hello Steve

You wrote:
" That plot was produced in an earlier schematic. I later encountered problems with the schematic no longer recognising .inc statements and hence refusing to work. "

Have you still the .log file you got when you tried to run the earlier schematic ?

Note that in
.SUBCKT 2SC6144SG 1 2 3
Q1 1 2 3? C6144SG??????????????????????????????????????????????????????????????
?????????????????????????????????????????????????????????????????????????????
.MODEL C6144SG npn (?????? IS?????? = 3.500p???????? BF?????? = 335??????????
+NF?????? = 1????????????? VAF????? = 9????????????? IKF????? = 13???????????
+ISE????? = 50.00p???????? NE?????? = 2????????????? BR?????? = 160??????????
+NR?????? = 1????????????? VAR????? = 26???????????? IKR????? = 2.9??????????
+ISC????? = 230.0p???????? NC?????? = 2????????????? RB?????? = 910.0m???????
+IRB????? = 100.0m???????? RBM????? = 22.20m???????? RE?????? = 20.50m???????
+RC?????? = 3.300m???????? XTB????? = 1.9??????????? EG?????? = 1.11?????????
+XTI????? = 3????????????? CJE????? = 1.420n???????? VJE????? = 750.0m???????
+MJE????? = 383.0m???????? TF?????? = 450p?????????? XTF????? = 7????????????
+VTF????? = 1.000K???????? ITF????? = 20???????????? PTF????? = 0????????????
+CJC????? = 230.0p???????? VJC????? = 520.0m???????? MJC????? = 418.0m???????
+XCJC???? = 1????????????? TR?????? = 1.000n???????? FC?????? = 500.0m???????
+KF?????? = 0????????????? AF?????? = 1????????????? )???????????????????????
*????????????????????????????????????????????????????????????????????????????
.ENDL 2SC6144SG

.ENDL? should be ENDS

LTspice can't run with .endl

Regards
PhB
Re: Takes two day for my post to show up

[email protected]
 

Just for the record, Yahoo Messenger, the pioneer among Instant messaging will be dead from today and will no longer supported, I have been Yahoo Messenger user for over 10 yrs and will loose all my worldwide contacts...!!!!
CRIES..
AG
Re: Takes two day for my post to show up

[email protected]
 

Just for the record, Yahoo Messenger , one of the pioneers in Instant Messaging is shutting down as of today,, I have been a ?user for over 10 years and will loose my world wide contacts... Compare that to Skype which ?changed hands to Microsoft....
Cries
AG
Re: Probing phase

Steve Kale
 

¿ªÔÆÌåÓý

Actually I just now found the problem with the missing model definition statement although I don¡¯t understand why it is one. ?In my older schematic I had, at one stage, wanted to test the impact of a different pass transistor and rather than use a .inc statement for this new transistor¡¯s subcircuit statement I had pasted it directly into the circuit (see below). ?If I make it a comment, I no longer get the error message in relation to the missing model statement for Qd44vh10. ?If I make it a Spice directive I do - even though I am not using the subcircuit at all in the sim and the error doesn¡¯t relate to the 2sc6144sg at all. ?

???

Now, the sub 1kHz behaviour remains the same as the image I had uploaded in the zip file (i.e. different from my new circuit) so I need to track down what¡¯s causing that difference.



2SC6144SG SPICE PARAMETER ***
* DATE : 2015/03/13 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??
* Temp = 27 deg

.SUBCKT 2SC6144SG 1 2 3
Q1 1 2 3 ?C6144SG ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??
.MODEL C6144SG npn ( ? ? ? IS ? ? ? = 3.500p ? ? ? ? BF ? ? ? = 335 ? ? ? ? ??
+NF ? ? ? = 1 ? ? ? ? ? ? ?VAF ? ? ?= 9 ? ? ? ? ? ? ?IKF ? ? ?= 13 ? ? ? ? ? ?
+ISE ? ? ?= 50.00p ? ? ? ? NE ? ? ? = 2 ? ? ? ? ? ? ?BR ? ? ? = 160 ? ? ? ? ??
+NR ? ? ? = 1 ? ? ? ? ? ? ?VAR ? ? ?= 26 ? ? ? ? ? ? IKR ? ? ?= 2.9 ? ? ? ? ??
+ISC ? ? ?= 230.0p ? ? ? ? NC ? ? ? = 2 ? ? ? ? ? ? ?RB ? ? ? = 910.0m ? ? ? ?
+IRB ? ? ?= 100.0m ? ? ? ? RBM ? ? ?= 22.20m ? ? ? ? RE ? ? ? = 20.50m ? ? ? ?
+RC ? ? ? = 3.300m ? ? ? ? XTB ? ? ?= 1.9 ? ? ? ? ? ?EG ? ? ? = 1.11 ? ? ? ? ?
+XTI ? ? ?= 3 ? ? ? ? ? ? ?CJE ? ? ?= 1.420n ? ? ? ? VJE ? ? ?= 750.0m ? ? ? ?
+MJE ? ? ?= 383.0m ? ? ? ? TF ? ? ? = 450p ? ? ? ? ? XTF ? ? ?= 7 ? ? ? ? ? ??
+VTF ? ? ?= 1.000K ? ? ? ? ITF ? ? ?= 20 ? ? ? ? ? ? PTF ? ? ?= 0 ? ? ? ? ? ??
+CJC ? ? ?= 230.0p ? ? ? ? VJC ? ? ?= 520.0m ? ? ? ? MJC ? ? ?= 418.0m ? ? ? ?
+XCJC ? ? = 1 ? ? ? ? ? ? ?TR ? ? ? = 1.000n ? ? ? ? FC ? ? ? = 500.0m ? ? ? ?
+KF ? ? ? = 0 ? ? ? ? ? ? ?AF ? ? ? = 1 ? ? ? ? ? ? ?) ? ? ? ? ? ? ? ? ? ? ? ?
* ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??
.ENDL 2SC6144SG ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??
* ?Information herein is for example only; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
* ?it is not guaranteed for volume production. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??
* ON Semiconductor

On 9 Aug 2016, at 11:11, Steve ?wrote:

I have poured over the two schematics including all value/spice line statements (CTRL-left click on a device) and can see no differences. ?I can¡¯t run the old schematic at the moment as I¡¯m currently getting an error ¡°missing model definition for QD44VH10¡± even though I clearly have the .inc statement for the model file (I have even deleted the Spice directive - it¡¯s not a comment - and added it again) and CTRL-left click on every QD44VH10 device reveals exactly the same as the new file I posted. (Both .asc files sit in the same folder and so both have access to the same model text file.) I will go back to it at some point (and may even check older versions via Mac¡¯s Time Machine facility) as I do want to see if the sub 1k behaviour remains the same. ?
Re: No XP?

 

Hello Rick,

The reason is simple.
Mike cannot support XP with the latest Microsoft and Intel compiler tools. These tools only support WIN 7 and newer operating systems.

Best regards,
Helmut
Re: Probing phase

Steve Kale
 

¿ªÔÆÌåÓý


On 9 Aug 2016, at 07:17, Andy wrote:


It can't be either/or.? It must be only one of them, depending on how you have kept track of polarities.? Phase margin can be >90 degrees, so it's not the one that is closer (which forces it to be <90 degrees).

The fact that you added a minus sign to the thing being plotted, adds -180 degrees to the phase plot.


Duh. ?The first point makes sense. ?I¡¯ve clearly been getting confused between the graph portraying phase (excluding the op amp's 180 degrees) and phase margin directly. Plus the impact of the minus sign. ?Of course, in the example I posted, if it is not applied then the graph would read +89 degrees. If it is then the graph reads -91 degrees. It seems odd to talk about a negative margin but Helmut had some time ago told me to plot with the minus sign.

??

? ?"[Incidentally, a few days ago LTspice produced the plot in Phase and Gain Margin - old.jpg. ...
? ? At this stage I can only (very gingerly) conclude that this resulted from the update to LTspice.? Eek...]"

It's very unlikely.

There probably was a difference between your circuits.? But they can be hard to find.? Sometimes, comparing the .net files makes it easier to find their differences.

One problem with visually comparing schematics, is that attributes can be made not visible.

? ?"...?problems with the schematic no longer recognising .inc statements ..."

That should not have happened either, and points to something being wrong in the schematic, or with the included files themselves.? Typo?


I have poured over the two schematics including all value/spice line statements (CTRL-left click on a device) and can see no differences. ?I can¡¯t run the old schematic at the moment as I¡¯m currently getting an error ¡°missing model definition for QD44VH10¡± even though I clearly have the .inc statement for the model file (I have even deleted the Spice directive - it¡¯s not a comment - and added it again) and CTRL-left click on every QD44VH10 device reveals exactly the same as the new file I posted. (Both .asc files sit in the same folder and so both have access to the same model text file.) I will go back to it at some point (and may even check older versions via Mac¡¯s Time Machine facility) as I do want to see if the sub 1k behaviour remains the same. ?However, for now I have just moved on as I am most focused on how to appropriately probe the circuit for the loss of phase margin. I want to understand how each piece of the circuit degrade phase margin beyond the 180 degrees from the op amp. ?Of course, when I don¡¯t have confidence I am using LTspice properly in this regard it becomes rather hard to have confidence in the results.?


Sorry, your questions are very complicated and it's late.? I'll try to write more later.

Andy

I very much appreciate it Andy.

I¡¯m also focused on ¡®disconnects¡¯** between the two forms of analysis: ?top circuit AC injection at Vin and modelling Vout vs freq for line rejection and bottom circuit loop gain and phase analysis. ?If, for example, I make a change to the output caps in the bottom circuit such that UGF is extended (output cap pole or zero is affected) and/or greater loop gain is applied I would expect the identical change in the top circuit to extend the line rejection in similar fashion (greater feedback being applied or being applied to higher frequencies). ?Yet it doesn¡¯t.?

** disconnects that may well be just my lack of knowledge


regards

Steve
Re: PWL file in LTSPICE XVII not working while working in LT spice IV

 

Hello,

Mike told me that he will fix this PWL problem in the 32bit version in the next release.

Best regards,
Helmut
Re: PMBFJ620/2SK2145 or any other dual JFET-models exist for LTspice?

 

Thanks! I'll give these a try. :)
Re: PMBFJ620/2SK2145 or any other dual JFET-models exist for LTspice?

 

Hi.
.MODEL KPS104A NJF VTO=-0.4 BETA=0.002 LAMBDA=0.005 RD=20 RS=15 IS=1.145e-13 CGD=1.2p CGS=4p PB=0.5 B=1 KF=5e-18 AF=0.5 FC=0.5 MFG=USSR
.MODEL KPS104V NJF VTO=-0.9 BETA=0.0015 LAMBDA=0.008 RD=20 RS=15 IS=1.145e-13 CGD=1.2p CGS=4p PB=0.5 B=1 KF=5e-18 AF=0.5 FC=0.5 MFG=USSR
.MODEL KPS104G NJF VTO=-1.5 BETA=0.001 LAMBDA=0.01 RD=20 RS=15 IS=1.145e-13 CGD=1.2p CGS=4p PB=0.5 B=1 KF=5e-18 AF=0.5 FC=0.5 MFG=USSR

.MODEL LSK389A NJF BETA=0.0378643 VTO=-0.4025156 LAMBDA=4.783719m IS=3.55773E-14 N=1 RD=10.6565 RS=6.8790487 CGD=3.99E-11 CGS=4.06518E-11 PB=0.981382 MJ=0.794653 FC=0.5 KF=5e-18 AF=1
.MODEL LSK389B NJF BETA=0.0350699 VTO=-0.5375582 LAMBDA=4.951m IS=2.76212E-14 N=1 RD=7.82168 RS=6.9525888 CGD=4.36E-11 CGS=4.36E-11 PB=1.2 MJ=0.8892205 FC=0.5 KF=5e-18 AF=1
.MODEL LSK389C NJF BETA=0.0278541 VTO=-0.800434 LAMBDA=0.0122435 IS=2.45217E-14 N=1 RD=12 RS=5.8 CGD=4.22E-11 CGS=4.23E-11 PB=0.9265487 MJ=0.6098477 FC=0.5 KF=4e-18 AF=1

.MODEL 2SK389BL NJF (VTO=-2.5 BETA=6M LAMBDA=1.2M RD=4.95 RS=4.45 IS=6.32F PB=1 FC=.5 CGS=71.2P CGD=18.9P)
.MODEL 2SK389 NJF (VTO=-2 BETA=20M LAMBDA=600U RD=7 RS=6.3 IS=1.58F PB=1 FC=.5 CGS=19.5P CGD=5.5P)

.model J2SK389BL NJF (Vto=-2.5 Beta=6m Lambda=1m2 Rd=4.95 Rs=4.45 Is=6f32 Pb=1 Fc=.5 Cgs=71p2 Cgd=18p9

Bordodynov.


09.08.2016, 11:12, "rickard.steffensen@... [LTspice]" <ltspice@...>:

As topic states, im looking for dual JFET-models. Must be something out there?

Regards,

Rickard
Re: No XP?

Gunoi Nare
 

A better solution would be to Install VBOX from ORACLE.
G.


From: "Andy ai.egrps@... [LTspice]"
To: [LTspice] group
Sent: Monday, August 8, 2016 12:33 AM
Subject: Re: [LTspice] Re: No XP?

?
Craig wrote:

? ?"
?
Maybe someone who's locked into XP could try dual-booting with Linux to run LTspice and let us know how it goes."

I'm pretty sure at least two people here have already reported that LTspiceXVII does run in Linux with Wine emulating XP.

I contend that Wine emulating XP is not 100% the same as Microsoft Windows XP, so to me at least, it's not surprising if it runs differently on an XP-emulator than on XP itself.

Andy
Re: No XP?

Gunoi Nare
 

Well said.

Live Long and Prosper.
G.


From: "iamrogerholden@... [LTspice]"
To: LTspice@...
Sent: Monday, August 8, 2016 4:28 AM
Subject: [LTspice] Re: No XP?

?
I am seriously concerned about the implications of this thread, I only use XP as it is compatible with all my other tools, does not randomly crash/freeze up and is no longer patched/botched by microsoft so is actually stable. I have no intention of installing later malware into my machines. I don't care about running the latest & greatest LTspice either but will the XT compatible IV continue to be available and do I have to prevent LTspice updates to avoid an automatic XVII installation ?
PMBFJ620/2SK2145 or any other dual JFET-models exist for LTspice?

 

As topic states, im looking for dual JFET-models. Must be something out there?


Regards,

Rickard
Re: Probing phase

 

Steve wrote a rather lengthy message, including:

? ?"I read phase margin as the absolute difference between the reading for phase at the UGF and 0 or 180/-180 whichever is closer."

It can't be either/or.? It must be only one of them, depending on how you have kept track of polarities.? Phase margin can be >90 degrees, so it's not the one that is closer (which forces it to be <90 degrees).

The fact that you added a minus sign to the thing being plotted, adds -180 degrees to the phase plot.

? ?"[Incidentally, a few days ago LTspice produced the plot in Phase and Gain Margin - old.jpg. ...
? ? At this stage I can only (very gingerly) conclude that this resulted from the update to LTspice.? Eek...]"

It's very unlikely.

There probably was a difference between your circuits.? But they can be hard to find.? Sometimes, comparing the .net files makes it easier to find their differences.

One problem with visually comparing schematics, is that attributes can be made not visible.

? ?"...?problems with the schematic no longer recognising .inc statements ..."

That should not have happened either, and points to something being wrong in the schematic, or with the included files themselves.? Typo?

Sorry, your questions are very complicated and it's late.? I'll try to write more later.

Andy
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