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In message <l84jdn+uq5msk@...>, dated Mon, 9 Dec 2013, aymen.dardouri1990@... writes: It can be done in some cases, but it's not easy in most cases and near impossible in others. You

Hallo, I'm trying to simulate a new project using very specific components, but i had a huge problem in finding the right spice models, i've loooked everywhere but in vain, i've been told the is a

I understand that. Yet it's a limitation. I'm not questioning the validity of the explanation. I was just attempting to explain why why some users don't like that. If I'm not mistaken, some other sim

Rick, How did you manage to get three digits of resolution? I tried using the cursor but could not locate 0dB or measure the phase angle that accurately. I assume you used the .measure command - could

Jerry, This is not a SPICE or LTspice limitation.? If you had to solve a circuit with a bunch of nodes isolated from ground and wanted to solve the voltages at all the nodes, you couldn't do it,

Hello, You can figure out how to apply loopgain analysis to this circuit by considering the base of the input transistor as the positive input to a differential amp and the emitter of it as the

John, Yes, we are looking at different files. I looked at the one posted by vegetat55 to the temp folder. It is an .asc file but the extension doesn't show up so I had to save it, and rename it to add

In message <l82jov+1092dt7@...>, dated Sun, 8 Dec 2013, sawreyrw@... writes: We must be looking at different .asc files. I'm looking at one that just has MCP6292 op-amps and a few Rs

well what i want to do is to evaluate the circuit's gain and phase margins as described in ltspice educational examples Loopgain.asc ,Loopgain2.asc .But with this kind of topology i post,i dont know

John, R1 is a bias resistor to ensure Q2s collector current is sufficient. It also provides a path to discharge Q7s base when the AC voltage swings down. C1 reduces the bandwidth of Q7. Rick

In message <l82hrs+nqehh0@...>, dated Sun, 8 Dec 2013, vegetat55@... writes: What are C1 and R1 for? If you disable this network by making R1 = 1 meg, it seems to work as predicted.

the file i posted is at Files > Temp named Singleton amplifier loop gain simulation(Gain & phase margins).asc

In message <l82gt4+nphhn5@...>, dated Sun, 8 Dec 2013, vegetat55@... writes: Please upload the schematic, not the net list. It's far easier to help with a schematic. -- OOO - Own

Hello. I am trying to simulate the loop gain of this kind of amplifier but i cant. i want to find gain margin and phase margin.can you help? I uploaded LTspice file in temp folder here:

Le 08/12/2013 14:07, Andy a crit : I believe the reason is when a transformer is properly modelled with its stray capacitances, the results will be different in function of the way the floating part

Smart! I have never thought of doing that. I include additional files in some of my subcircuits/lib files, but I still have to .inc my subcircuit. I will try your trick!

Dhara wrote: Therefore I would like to specify two different grounds. Is this actually There's nothing stopping you from having any number of so-called "grounds" (in sloppy electrical circuit

Hello, You have most probably defined too high numbers in the symbol's "Netlist Order". These numbers should be 1,2,3,4,5,6,78 in the order of the .subckt line. I have uploaded two examples

you may right-click on the wire and chose "label", and there you have ground and com ... which is the one you seek.

I created the links, but instead of using a .inc file, put the equivalent path into the custom symbol for the path to the MyLib. Your help is much appreciated, thanks.